CPU Structure: CU, ALU, Registers

Why I Started Studying CPU Structure

When you write code, sometimes you wonder, "Why is this so slow?" The profiler points to a specific function, but the algorithm complexity looks fine. Then terms like "cache miss" and "branch prediction failure" start appearing, and you realize: to truly understand performance, you need to know what happens inside the CPU.

So I decided to take the CPU apart — conceptually, not physically.

What Confused Me at First

I thought the CPU was just "a fast calculator." Plug in electricity, get addition. Simple.

But looking at the actual structure, it's more intricate than expected:

• Why are the Control Unit and ALU separated?
• How are registers different from RAM?
• What exactly does the "clock" do?

Trying to understand everything at once was overwhelming, so I settled on a metaphor: the CPU is a factory.

The Aha Moment: "The CPU is a High-Speed Factory"

Zoom into a CPU under a microscope, and you'll find a vast city inside. The easiest way to grasp it is by thinking of a factory with three key members:

• The Manager (Control Unit): gives work orders
• The Worker (ALU): actually builds things
• The Workbench (Registers): the desk where immediate materials and tools sit

These three are essentially the entire CPU. Everything else is a variation or optimization of this structure.

1. Control Unit (CU): The Manager

Think of an orchestra conductor. The CU fetches instructions from memory, decodes them, and issues orders to each component.

• "Hey Memory! Fetch data at address 100."
• "Hey ALU! Add these two numbers."
• "Hey Register! Save this result."

It doesn't do the heavy lifting, but it controls the entire flow. The Manager.

More specifically, the Control Unit:

1. Fetches the next instruction from memory.
2. Decodes machine code like 0x1A into "Ah, this means ADD."
3. Generates control signals — electrical signals telling the ALU to "add" or registers to "store."

Without the CU, even the fastest ALU wouldn't know what to calculate. It's a factory full of workers with no one telling them what to build.

2. ALU (Arithmetic Logic Unit): The Worker

This is where the actual computation happens. The ALU handles two kinds of operations:

Arithmetic Operations:

• Addition, subtraction, multiplication, division
• This is where the adders and logic gates we studied earlier live

Logic Operations:

• AND, OR, NOT, XOR
• Comparisons (Is A greater than B?)

The ALU itself is simple. "Addition complete, boss." "Comparison done." It silently computes whatever it's told. The Worker.

But modern ALUs aren't just simple adders. They contain a dedicated FPU (Floating Point Unit) for decimal math, and SIMD (Single Instruction, Multiple Data) units that process multiple data points with a single instruction — a huge boost for image processing and scientific computation.

3. Registers: The Workbench

Ultra-fast temporary memory for the CPU. If RAM is a 'bookshelf', registers are the 'desk'.

Walking to the bookshelf every time wastes time. So we put the numbers we need right now on the desk (registers) to work fast.

Key Register Types

General Purpose Registers: Temporary boxes for data being calculated. On x86: EAX, EBX, ECX, EDX. On ARM: R0–R15.

Special Purpose Registers:

• PC (Program Counter): "Which bookshelf slot is next?" — stores the address of the next instruction.
• IR (Instruction Register): "What's in the book I'm reading?" — holds the current instruction.
• ACC (Accumulator): "Keep the result here for now." — stores intermediate values.
• MAR (Memory Address Register): holds the address to read from or write to in memory.
• MDR (Memory Data Register): holds data read from or to be written to memory.
• SP (Stack Pointer): points to the top of the call stack — critical for function calls and returns.
• PSW/FLAGS: records the status of the last operation (positive? negative? zero? overflow?).

Speed Comparison: Why Registers Matter

Memory Type	Access Time	Analogy
Register	~0.3ns	Sticky note on your desk
L1 Cache	~1ns	Inside your desk drawer
L2 Cache	~3–10ns	Bookshelf in the same room
RAM	~50–100ns	Library at the end of the hallway
SSD	~100,000ns	Warehouse in another building

Registers are over 200x faster than RAM. If the CPU had to travel to RAM for every operation, performance would collapse. That's why the CPU loads only the data it needs immediately into registers, computes, then writes results back to memory.

4. The Heartbeat: Fetch-Decode-Execute Cycle

From the moment a CPU powers on until it shuts down, it repeats one loop: the FDE (Fetch-Decode-Execute) cycle, billions of times per second.

Step 1: Fetch

• Read the instruction at the memory address pointed to by the PC.
• Store it in the IR (Instruction Register).
• Increment the PC to point to the next instruction.

Step 2: Decode

• The CU reads the instruction in the IR.
• "0x1A? That's an ADD instruction."
• It identifies the operands: "Add registers R1 and R2."

Step 3: Execute

• The CU sends control signals to the ALU.
• The ALU performs the operation (R1 + R2).
• The result is written back to the designated register or memory location.

These three steps process one instruction. Even a simple line like a = b + c; requires multiple FDE cycles: load b into a register, load c, add them, store the result at a's memory address.

Clock and GHz

The clock determines the speed of this cycle. It's like a metronome sending "tick, tick, tick" signals at regular intervals.

• 1 GHz = 1 billion ticks per second
• 4 GHz = 4 billion ticks per second

Each tick advances one stage of the FDE cycle (in practice, pipelining makes this more complex, but the principle holds). When we say a CPU is "fast," we mean this factory runs billions of cycles per second.

5. Design Philosophies: CISC vs RISC

When designing a CPU, there's a fundamental philosophical divide: "Should instructions be complex or simple?"

CISC (Complex Instruction Set Computer) — Intel x86

Philosophy: "One instruction should do a lot."

• A single instruction can read from memory, compute, and store — all in one go.
• Pros: Smaller code size. Hardware does the heavy lifting so the compiler has less work.
• Cons: Complex circuitry. High power consumption. Heat issues.
• Used in: Desktop PCs, servers (Intel, AMD).

RISC (Reduced Instruction Set Computer) — ARM

Philosophy: "Keep instructions as simple as possible."

• Only basic operations: Load, Store, Add, Compare.
• Complex tasks are built by combining simple instructions.
• Pros: Simpler circuits, better power efficiency, great for pipelining.
• Cons: More instructions needed for the same task (compiler works harder).
• Used in: Mobile phones, Apple M-series MacBooks, RISC-V.

The Real-World Convergence

Here's the interesting thing: this distinction is blurring. Intel's x86 CPUs accept CISC instructions on the surface but internally translate them into RISC-style micro-ops for execution. Apple's M1/M2 chips are RISC-based (ARM) but deliver desktop-class performance with exceptional power efficiency.

It's not about "which is better" — it's a trade-off based on use case:

• Servers/desktops with plentiful power → CISC (x86) for compatibility and ecosystem
• Mobile/embedded where battery matters → RISC (ARM) for power efficiency

CPU = A Smart Idiot

As you can see, the CPU isn't a creative brain. It's a mechanical factory where the Manager (CU) orders the Worker (ALU) to crunch data on the Desk (Registers).

But because this factory runs billions of times per second (GHz), it looks like genius to us.

Key Takeaways

Every time you type if, for, or +, this factory goes into emergency mode. The Manager yells, the Worker sweats, the Workbench reshuffles.

Understanding CPU structure makes a few things click:

• Why local variables are fast: they're likely loaded into registers.
• Why branching (if/else) has a cost: it breaks the pipeline and wastes FDE cycles.
• Why cache-friendly code matters: memory access is 200x slower than register access.

If your code is slow, ask yourself: Am I running this factory inefficiently? (e.g., unnecessary memory accesses, branch-heavy logic, poor data locality)