F·17COMPUTER SCIENCE2025.02.041 MIN READ
Cache Memory Hierarchy (L1, L2, L3): The Art of Making Every Second Count 100x
캐시 메모리(L1, L2, L3)와 지역성: 1초를 100배로 쓰는 기술 (완전정복)
90% of CPU performance is determined by cache. From data locality and MESI protocol to cache mapping, TLB, branch prediction, and NUMA.
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INTERDISCIPLINARY DEV · SEOUL
9. Memory Hierarchy Summary
| Level | Name | Size (Typical) | Speed (Cycles) | Analogy (Kitchen) | Role |
|---|
| L0 | Registers | < 1KB | 0 | Chef's Hands | Active Calculation |
| L1 | L1 Cache | 32KB ~ 64KB | 4 | Cutting Board | Immediate Data |
| L2 | L2 Cache | 256KB ~ 2MB | 12 | Countertop | Private Backup |
| L3 | L3 Cache | 8MB ~ 64MB | 40 | Shelf | Shared Data |
| MEM | DRAM | 16GB ~ 64GB | 200+ | Walk-in Fridge | Workspace Storage |
| DISK | SSD/HDD | > 512GB | Millions+ | Grocery Store | Long-term Storage |
| TLB | TLB | 96~ Entries | 0~1 | Phonebook | Translation Cache |